The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a 3-dimensional nonvolatile memory device and a method of manufacturing the same.
A nonvolatile memory device is a kind of memory device, which is capable of intactly retaining stored data without power supply. As a two-dimensional memory device manufactured as a single layer on a silicon substrate may be reaching a technical limit for increasing integration density, a three-dimensional nonvolatile memory device, which includes memory cells vertically stacked on a silicon substrate has been proposed recently.
Hereinafter, some concerns in conventional three-dimensional nonvolatile memory devices will be described in detail, with reference to the drawings.
FIG. 1 is a cross-sectional view of a conventional 3-dimensional nonvolatile memory device.
Referring to FIG. 1, the conventional 3-dimensional nonvolatile memory device may include channels CH protruding from a substrate 10 and a plurality of memory cells MC stacked along the channels CH. Also, the memory device may further include a lower selection gate LSG formed under the plurality of memory cells MC and an upper selection gate USG formed on the plurality of memory cells MC. Bit lines BL may be provided on the upper selection gate USG. The bit lines BL are connected to the channels CH. In the above-described structure, a plurality of memory cells MC connected in series between the lower selection gate LSG and the upper selection gate USG may constitute one string STRING, which may locate vertically on the substrate 10.
In FIG. 1, reference numerals 11, 14, and 17 denote interlayer insulating layers. A reference numeral 12 denotes a lower selection line. Reference numeral 15 denotes a word line. A reference numeral 18 denotes an upper selection line. Also, reference numerals 13 and 19 denote gate insulating layers. A reference numeral 16 denotes a charge blocking layer, a charge trap layer, and a tunnel insulating layer.
A method of forming the memory cells CH is briefly described. A plurality of conductive layers 15 and a plurality of interlayer insulating layers 14 may be alternately formed and etched in order to form trenches. Thereafter, a charge blocking layer, a charge trap layer, and a tunnel insulating layer 16 may be formed on inner walls of the trenches. A channel layer may be formed in the trenches. Due to the above-described manufacturing process, charge trap layers of the plurality of memory cells MC stacked along the channels CH may be connected to one another.
Here, the charge trap layer may serve as a substantial data storage where data is stored by injecting or emitting charges. In the conventional structure where the charge trap layers of the memory cells MC are connected to one another, charges stored in one memory cell MC may be moved or transported to another memory cell MC so that stored data may be changed or damaged.